英 [ˈraɪzɪŋ edʒ] 美 [ˈraɪzɪŋ edʒ]
上升沿：在电子学中，信号边缘（英语：signal edge），或称信号边沿，是数字信号在两种逻辑电平（0或1）之间状态的转变。由于数字信号电平由方波来表示，因此这种状态的变化被称为“边缘”。
上升沿-引用次数：14
Meanwhile,it proposes that using an electronic switch to transfer two channels to generate square signal with fast rising edge and fall edge.
针对理想方波信号包含无穷频率分量、可用于动态特性测试的特点,提出了采用单刀双掷电子开关切换两路电平生成方波信号的实现方法,具有上升沿和下降沿速度快的优点。
上升边沿
上升缘
上升沿-引用次数：6
Because the width of the rising edge of each input pulse is 30 to 100ns, in order to gain the entire pulse signal, higer sampling speed is needed.250MHz was chosen as sampling speed.
由于输入脉冲信号的上升沿宽度为30～100ns，因此为了得到完整的脉冲信号，需要较高的采样频率，我们选用250MHz采样频率。
上升边缘
而且，在单向汇流排里，资料在时钟的上升沿（rising edge） 或者下降沿被锁存，而在双向汇流排里，资料在控制器（strobe）的两个变化沿被锁存。 表1.
如果在上升边缘(Rising Edge) 上，电压超过逻辑高位准(Voltage High)，我们称之为Overshoot。
上升缘（Rising Edge）: 前一个 Clock 是低准位，这一个 Clock 是高准位。
... 股价上涨 ballooning 上涨沿 rising edge 直线上涨 zoom up ...
[电子]前沿；上升边
If a mark is to be transmitted, the output goes high after the rising edge of the clock.
如果一个标志是要传输时，输出变为高电平后，在时钟的上升沿。
Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.
数据读取连续的驱动ic的输入时钟的上升沿一旦机顶盒输入线变低。
Phase Jitter: refers to the deviation of the FBKCLK rising edge to the REFCLK rising edge with respect to the average offset in a random sample of cycles.
相位抖动：指的是反馈时钟和参考时钟之间上升沿差异与多次随机采样的平均偏移之间的差。
At Richard Meier's two 15-story luminescent glass towers rising along the edge of New York City's Greenwich Village overlooking the Hudson River, the minimum apartment size is one floor-1, 800 square feet in the north building, 3, 700 in the south building.
At the same time, private consumption also lost some of its edge, rising 3.1% in 2012 from 4.1% in 2011.
Nani scored the second with a spectacular rising drive from the edge of the area nine minutes before the interval and Rooney, inevitably, was the man on the spot as United increased their lead in the closing seconds of the half.